As the parameter counts of large AI models balloon at an exponential rate, the “information highways” inside data centers are facing unprecedented pressure. High-speed copper interconnects, which have underpinned the computing industry for decades, are steadily giving way to a new generation of light-based interconnect technology under the triple squeeze of high bandwidth, low power, and longer reach. Heading into 2026, silicon photonics and co-packaged optics (CPO) are accelerating from the lab to mass production, becoming one of the most closely watched technology bellwethers in the chip industry. This article explains the deeper logic behind “copper retreating as light advances,” maps the redistribution of value across the supply chain, and explores what it means for Singapore's ecosystem and the SGX-listed technology sector.
Why Light: Three Interconnect Bottlenecks in AI Clusters
Modern AI data centers have scaled from thousand-GPU clusters to 100,000 GPUs and beyond, and every gradient synchronization between GPUs relies on moving massive amounts of data. Traditional pluggable optical modules solved long-distance transmission between racks, but at the new scale they expose three bottlenecks.
- Bandwidth density bottleneck: Bandwidth demand per accelerator card is evolving from 1.6T toward 3.2T and beyond, while the physical density of pluggable modules on the faceplate is approaching its limit, sharpening the conflict between port count and throughput.
- Power bottleneck: In traditional architectures, long traces between optical modules and switch chips plus DSP retiming circuits consume substantial power; the share of optical interconnect power in hyperscale clusters keeps climbing, directly squeezing the effective compute budget.
- Signal integrity bottleneck: Electrical signals attenuate at high frequencies in copper media. When per-lane speeds rise above 200G, pluggable solutions must rely on complex equalization and retiming, driving up latency and cost together.
Light's fundamental advantages: photons barely interfere with one another, transmission loss is extremely low, and bandwidth is far less distance-dependent than with electrical signals. That is why moving the optical engine as close as possible to the switch chip — even packaging them together — has become the industry's recognized direction.
Silicon Photonics and CPO: Bringing the “Optical Engine” into the Package
The core of silicon photonics is using mature CMOS processes to integrate optical components such as waveguides, modulators, and photodetectors on a silicon substrate, making “building optical chips” as scalable as building electronic ones. Co-packaged optics goes a step further: packaging the optical engine on the same substrate as the switch chip or XPU, shrinking high-speed copper traces that once ran tens of centimeters down to the millimeter scale, improving power, latency, and bandwidth density all at once.
Three Leaps of CPO over Traditional Approaches
- Power restructuring: In pluggable designs, SerDes must drive longer traces and perform retiming; CPO compresses this link inside the package, which the industry widely believes saves substantial relay power and frees more of the power budget for compute itself.
- Reliability design: The external laser source (ELS) architecture separates relatively short-lived, temperature-sensitive lasers from the optical engine, making them easier to maintain and replace and significantly improving system-level availability.
- Density leap: Measured by “throughput per square millimeter,” CPO delivers bandwidth density far beyond faceplate-level pluggable solutions, paving the way for 3.2T and even 6.4T-generation switch chips.
The Roadmap Battle: CPO, LPO, and Enhanced Pluggables in Parallel
Notably, technological evolution is not a single-track path. LPO (linear-drive pluggable optics) removes the DSP to cut power and, thanks to its serviceability advantages, is landing first in some short-reach scenarios; enhanced pluggable solutions keep compressing power and cost within the traditional form factor. CPO represents the long-term direction, but until yield, testing, and field-service systems mature, multiple routes will coexist for a long time. This “multi-track parallel” landscape is precisely the key frame of reference for judging the pace at which each link of the supply chain benefits.
Supply Chain Moves: Value Redistribution from Switch Chips to Optical Modules
Over the past two years, major global players have already positioned themselves around this direction: the networking chip leader has launched switch platforms with integrated CPO, bringing optical engines directly into the 51.2T generation; the foundry leader is advancing an optoelectronic co-packaging process platform with an evolution roadmap running from optical engines and optoelectronic integrated chips to co-packaged substrates; interconnect IP and Chiplet vendors are shifting focus toward chiplet-based optical interfaces. Traditional optical module leaders, while consolidating the pluggable market, are accelerating their transformation into optical engine and CPO component suppliers. The redistribution of the value chain shows clear layers.
- Upstream: Heterogeneous integration processes that bond III-V lasers with silicon (bonding, interposers) have become the core step, and related equipment and materials suppliers benefit from new production-line investment.
- Midstream: Advanced packaging capacity capable of optoelectronic co-packaging has become a scarce resource, and stricter requirements for cleanliness and alignment precision significantly raise the value of the testing stage.
- Downstream: Cloud providers and supercomputing centers are CPO's first adopters, and their capital-expenditure rhythm directly determines how fast the technology penetrates.
The Singapore Perspective: A Hub Ecosystem and a Window into the SGX Technology Sector
For Singapore, this interconnect shift carries special significance. As a leading global data center hub and semiconductor manufacturing base, Singapore's local research institutions have deep expertise in optoelectronic integration and heterogeneous packaging, and its advanced packaging and testing capacity is a key pivot in the regional supply chain. Meanwhile, the regional data center expansion driven by Southeast Asia's “digital corridor” build-out will continue to fuel demand for high-speed optical interconnects. Although SGX currently lacks pure-play silicon photonics listings, the industry mapping logic is clear: locally listed semiconductor equipment, packaging and testing, and electronics manufacturing services companies could all benefit indirectly through global customers' optoelectronic product orders; the demand-side logic of regional data center and telecom infrastructure assets also resonates in the same direction as compute interconnect expansion. For investors, “optical interconnect penetration” is a new dimension worth adding when tracking the health of the SGX technology sector.
Challenges and Risks: Four Hurdles Between Ideal and Reality
- Yield and cost: Yield ramp-up for hybrid optoelectronic packaging is slow, and initial costs are clearly higher than mature pluggable solutions; the cost-performance inflection point still needs time to prove itself.
- Serviceability: Packaging the optical engine together with core chips means a failure may require replacing the entire package, and both field repair processes and spare-parts systems need to be rebuilt.
- Standards and ecosystem: Interface standards and test specifications for optoelectronic co-packaging are still being refined, and multi-vendor interoperability will require longer industry coordination.
- Demand pacing: If AI capital expenditure growth slows, the CPO mass-production ramp could be correspondingly delayed, amplifying valuation swings for related companies.
Conclusion: Put Optical Interconnects on Your 2026 Chip Watch List
The physical limits of Moore's Law have not yet been reached, but interconnect is becoming the new first-order constraint. The significance of silicon photonics and CPO is not just power savings or speed; it redefines the boundary of the “chip” — when optical engines are co-packaged with compute and switch cores, the future “single chip” will be both electrical and optical. For industry observers, 2026 offers three signals to watch closely: the shipping cadence of top switch-chip vendors' CPO platforms, customer adoption progress for foundries' optoelectronic co-packaging processes, and the financial realization of optical module makers' shift toward optical engine businesses. Copper retreating as light advances is not an overnight replacement but a gradual migration driven by AI compute demand — whoever finds the right position on the migration curve will hold the first-mover advantage in the next semiconductor cycle.
